1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a method for forming pillar memory cells.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in Dynamic Random Access Memory (DRAM) markets. DRAM devices are used extensively in computer applications where large amounts of inexpensive yet relatively high performance memory is needed. As more advanced applications are developed, an increasing large amount of DRAM is needed. This has driven an ever increasing need for greater device densities and economical ways of producing these devices.
A typical DRAM chip is made of millions of individual DRAM "cells." Each cell contains a capacitor used to the memory charge, a switch used to access the capacitor, and some isolation regions around these devices. The individual cells are accessed using a large number of bit lines and word lines. By selecting an appropriate bit line and word line, a memory controller can access information contained in the desired DRAM cells.
The density of a DRAM chip is determined in a large part by the area needed for each DRAM cell. One particular area of concern in DRAM design is the storage capacitor used to store each memory cell. The density of DRAM designs is to a great extent limited to by the feature size of the storage capacitor. Capacitors by definition store charge between electrodes.
The charge stored in the storage capacitor is subject to current leakage and for that reason the DRAM must be refreshed periodically. The time allowed between refresh without excess charge leakage is the data retention time, which is determined by the amount of charge stored at the beginning of the storage cycle and the amount of leakage current through different kinds of leakage mechanisms. For various reasons it is often preferable to minimize the leakage mechanisms so as to extend the time allowed between refresh cycles.
Several methods have been used to facilitate the shrinkage of the cell feature size while maintaining sufficient capacitance. One of these methods is the use of pillar transistors with stacked capacitors located above the transistors, called a pillar DRAM cell. In one embodiment of a pillar DRAM cell the array channel device is bounded by an implant on the top of the pillar and by the buried plate at the base of the pillar. In another embodiment, the array channel device is bounded by an implant at the top of the pillar and a buried bitline. Today, these buried plates and bitlines are produced by filling the pillar structure with an organic material and recessing it back using an chemical etch process. The amount of recess controls the channel length of the transfer device which in turn determines the depth of the buried plate or bitline. Unfortunately, current methods of recessing the material typically result in significant nonuniformity as well as loading effects. This overall large tolerance results in channel length variation that can result in timing problems.
Additionally, because it is desirable to minimize shut off current in DRAM devices the transfer devices are typically designed with relatively long channels. This allows the transfer devices to be run far from the threshold voltage. Unfortunately, the lack of channel length uniformity resulting from current processes requires that devices be run at less than their optimal speed.
Thus, the prior art methods for forming plates and bitlines in pillar DRAM devices suffers from excessive nonuniformity, resulting in unwanted variations in channel length that can seriously degrade the performance of the devices.